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71M6545/71M6545H Data Sheet
When system power is not available, the 71M6545/H will be in SLP mode, if a battery is attached to the
VBAT_RTC pin.
Shortly after system power is removed (V3P3SYS < 3.0 VDC), VSTAT[2:0] will assume the value 001,
issuing a warning to the MPU. The IC can still operate in this state, however, the analog functions are not
considered accurate. Assuming that the recommended MPU setup code is resident in flash memory (see
2.4.1 MPU Setup Code on page 30 ), at V3P3SYS < 2.8 VDC, the 71M6545/H will be forced to SLP mode
by the MPU setting the SLEEP bit ( I/O RAM 0x28B2[7] ).
When system power is restored, the 71M6545/H will automatically transition from SLP mode back to MSN
mode.
Table 55: Available Circuit Functions
Circuit Function
Maximum MPU clock rate
System Power
MSN
CE Yes
FIR Yes
ADC, VREF Yes
PLL Yes
Battery measurement Yes
Temperature sensor Yes
4.92MHz
(from PLL)
MPU_DIV clock divider Yes
ICE Yes
DIO Pins Yes
Watchdog Timer Yes
V3P3D Pin Yes
VDD Pin Yes
EEPROM Interface (2-wire) Yes
EEPROM Interface (3-wire) Yes
UART (full speed) Yes
SPI slave port Yes
SPI Special Flash Mode Yes
Optical TX modulation Yes
Flash Read Yes
Flash Page Erase Yes
Flash Write Yes
RAM Read and Write Yes
OSC and RTC Yes
RAM data preservation Yes
NV RAM data preservation Yes
– indicates not active
Battery Power
SLP
--
--
--
Yes
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Yes
--
Yes
The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the
SLEEP bit. The purpose of the SLP mode is to consume the least power while still maintaining the RTC,
temperature compensation of the RTC, and the non-volatile portions of the I/O RAM.
In SLP mode, the V3P3D pin is disconnected, removing all sources of leakage from V3P3SYS. The non-
volatile memory domain and the basic functions, such as temperature sensor, oscillator, and RTC, are
powered by the VBAT_RTC input. In this mode, the I/O configuration bits and NV RAM values are
preserved and RTC and oscillator continue to run. This mode can be exited only by system power up.
If the SLEEP bit is asserted when system power is present, the 71M6545/H will still enter SLP mode. It
will drop WAKE, and then will begin the standard wake from sleep procedure.
After the transition from SLP mode to MSN mode the PC will be at 0x0000, the XRAM is in an undefined
state, and the I/O RAM is only partially preserved (see the description of I/O RAM states in 5.2). The non-
volatile sections of the I/O RAM are preserved unless RESET goes high.
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